Friday, October 16, 2009

SystemC TLM2.0 and SystemVerilog Verification Methodologies

TLM2.0 is the version 2.0 of Open SystemC (IEEE 1666) Initiative (OSCI) [1] standard and it is a layer on top of SystemC which itself is based on C++ language. TLM stands for Transaction-level Modeling which is an abstraction layer above RTL with the primary goal to accelerate simulation by avoiding detailed pin-level events that occur in RTL simulation.

In recent times, we have seen SystemVerilog based methodologies extend support for SystemC TLM2.0 standard. For example, Synopsys’ VMM Release 1.2 [2] supports TLM2.0 by adding remote procedure call functionality between components and extending support to SystemC modules.

TLM 2.0 is used in virtual platform models that are typically created to validate a system-on-a-chip (SoC) with multiple processor cores, busses, software stacks running on cores, and specialized digital and analog hardware IP blocks. These virtual platforms can accurately model functionality and registers in the SoC design without dealing with clocks and pins and are fast enough to boot software part of the system that may be available long before the creation of system RTL.

TLM provides mechanisms that can described as the glue that ties various IPs together in carrying out virtual platform simulation of the SoC. Some of the use cases of a virtual platform based on TLM are:
• Software Development
• Software Performance Evaluation
• Architectural Analysis
• Hardware Verification

The users of SystemVerilog based methodologies such as VMM leverage infrastructure and knowledge base to create verification needs for validating SoCs. The hardware verification task is similar to the virtual platform development in the sense that the verification works typically gets started even before the RTL may be available.

TLM2.0 core interfaces and sockets (mechanism for interoperability) can connect to VMM channels and notification. With the support of TLM2.0 in SystemVerilog based verification methodologies enables either building of or leveraging existing hardware verification environment early in the SoC design process that can be used to validate the SoC virtual platform model and then used later in validating the SoC at the RTL level.

Virtual platform that is created to accomplish key tasks of early software development, performance evaluation, and architectural analysis leverages and helps solidify a verification infrastructure based on SystemVerilog to be reused later in RTL validation also. Both the virtual platform and the verification teams can benefit from this connection.