Power management techniques that leverage voltage as a handle are being extensively used in power sensitive designs. These techniques include: Power Gating (PG), Power Gating with Retention (RPG), Multiple Supply Voltages (MSV), Dynamic Voltage Scaling (DVS), Adaptive Voltage Scaling (AVS), Multi-Threshold CMOS (MTCMOS), and Active Body Bias (ABB). The use of the power management techniques also imply new challenges in validation and testing of designs as new power states are created.
It is important that the lessons learned from validating power management of a design are captured as part of verification methodology and reused in later designs or future versions of the same design. Also, parts of established verification methodology can reused to address tasks needed in power management validation.
Power sequencing protocol is a good example of a task that appears in all power managed designs. Power sequencing typically follows a well-defined set of steps in designs that use power gating and state retention. These set of steps include:
• Disabling or gating the clock
• Saving state of registers in either special registers or in memory that is not powered off
• Enabling isolation for the block that has been powered off
• Disabling power to the block using a power switch
• Enabling power at the end of power gated mode
• Restoring saved register values
• Disabling isolation of the block
• Enabling the gated clock
This sequence or a simple variation sequence depending upon whether state retention is used or not is used in all power gated designs and potentially in different power-modes of the same design. The verification involves following a set of rules and routines to validate the sequence and can be part of infrastructure for verification of all power managed designs.
Another example can be the use of VMM Register Abstraction Layer (RAL) in the context of power management verification. VMM RAL is an application package to create abstract model of registers and memories inside a design that can used in the context of SystemVerilog based verification. It includes:
• Pre-defined tests to verify implementation of registers and memories
• Functional coverage model to ensure various bits of register have been tested
Power management software routines exercise various power modes of the design setting relevant bits in power control registers. VMM RAL can be used to manage this process through tests exercise various power modes through the setting of appropriate bits in power control registers and a coverage model can ensure that various power modes of the design have been exercised.
Power management verification should be seen as an extension of established verification methodology rather than a start from scratch. It does bring new elements like power-aware simulation (which can be seen as additional features in an existing simulator), dealing with specialized power-related signals and controls, and special power-related cells like switches, level-shifters, and isolation logic but these can be dealt with in the context of a verification methodology that builds upon an existing one.