In the past blog articles, we had focused on examples using VMM to discuss creation of a comprehensive verification methodology using SystemVerilog. The need for a common verification methodology has led to creation of Universal Verification Methodology (UVM) and an early adapter’s (EA) release was announced during the last DAC. This release can be downloaded from the Accellera website. Going forward, we will look into some of work and advances in UVM (as it moves to UVM 1.0 from the UVM EA release) as the work by an Accellera committee comprising of representatives from verification user companies such as Cisco, Freescale, Intel, and IBM along with the EDA companies including Cadence, Mentor, and Synopsys.
Some of the major areas of ongoing work include defining time-consuming phases in the simulation, register abstraction layer, and the TLM2 modeling.
Backward compatibility required that any additional time-consuming phases be run parallel to the run() phase defined in the EA release. SoC projects require a common test flow to ensure module-level environments easily integrate into the full-chip environment and the execution of simulation can move from one phase to another phase when all tasks (including all outstanding transactions) of the previous phase have completed. Being able to run these phases in parallel to the single run() phase defined in the EA release is the suggested way to make this enhancement.
Synopsys’ UVM Register Abstraction Layer (RAL) is an application package that can be used to automate the creation of object-oriented models of registers and memories inside a design. Janick Bergeron of Synopsys is leading the effort here that brings in years of earlier work done at Synopsys with SysytemVerilog VMM methodology work.
SystemC TLM2 standard is targeted to enable development of interoperable high-speed transaction-level models for virtual platforms in SystemC. These models need to memory-mapped bus-based systems at high speed such that software can be run on a virtual platform at near real-time speed. TLM2 is a complex standard and difficult to be mapped to languages other than SystemC. Some user-level requirements for a TLM2 implementation in UVM1.0 have been defined and they focus on TLM2 subset that includes generic payloads, blocking and non-blocking transport, and base protocols but no SystemC support.
We will look into some of these developments in more detail as the work on UVM advances at Accellera.